Voids-free Die-level Cu/ILD Hybrid bonding

Author:

Sakuma Katsuyuki1,Yu Roy1,Polomoff Nicholas1,Darling Luke1,Chowdhury Promod1,Raghavan Sathya1,Seifert Keodara1,Knickerbocker John1,McHerron Dale1,Li Ming2,So Siu Cheung2,Kwok So Ying2,Fan Chun Ho2,Lau Siu Wing2

Affiliation:

1. IBM T. J. Watson Research Center,Albany,NY,U.S.A.

2. ASMPT,Hong Kong

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. 3D Heterogeneous Integration with Sub-3μm Bond Pitch Chip-to-Wafer Hybrid Bonding;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. A Microstructural Investigation of Sub-1 μm Copper Bonding Contact Structures in Die-to-Wafer Hybrid Bonding;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

3. Elucidating the mechanism of four corner voids in chip-on-wafer hybrid bonding;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

4. State of the Art of Cu–Cu Hybrid Bonding;IEEE Transactions on Components, Packaging and Manufacturing Technology;2024-03

5. Cu-Cu Hybrid Bonding;Flip Chip, Hybrid Bonding, Fan-In, and Fan-Out Technology;2024

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