3D Heterogeneous Integration with Sub-3μm Bond Pitch Chip-to-Wafer Hybrid Bonding-Reference-Cited by-同舟云学术

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3D Heterogeneous Integration with Sub-3μm Bond Pitch Chip-to-Wafer Hybrid Bonding

Published:2024-05-28 Issue: Volume: Page:51-55
ISSN:
Container-title:2024 IEEE 74th Electronic Components and Technology Conference (ECTC)
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Author:

Shi Yi¹,Niazi Haris Khan¹,Rosshirt Michael A.¹,Paletti Saritha Kumari²,Brun Xavier F.¹

Affiliation:

1. Intel Corporation,Chandler,Arizona,USA

2. Intel Corporation,Hillsboro,Oregon,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10564841/10564831/10564956.pdf?arnumber=10564956

Reference14 articles.

1. Enabling Hybrid Bonding on Intel Process

2. 3D Packaging for Heterogeneous Integration

3. C2W Hybrid Bonding Interconnect Technology for Higher Density and Better Thermal Dissipation of High Bandwidth Memory

4. Extremely Large 3.5D Heterogeneous Integration for the Next-Generation Packaging Technology

5. Integrated Optical Interconnect Systems (iOIS) for Silicon Photonics Applications in HPC

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