A Convolution Neural Network Accelerator Design with Weight Mapping and Pipeline Optimization

Author:

Han Lixia1,Huang Peng1,Zhou Zheng1,Chen Yiyang1,Liu Xiaoyan1,Kang Jinfeng1

Affiliation:

1. Peking University,School of Integrated Circuits

Funder

National Natural Science Foundation of China

Publisher

IEEE

Reference23 articles.

1. Design efficient deep learning accelerator: Challenges and opportunities;emer;Proc VLSI Short Course,2017

2. A ferroelectric FET based power-efficient architecture for data-intensive computing

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4. PRIME

5. ISAAC

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1. CoMN: Algorithm-Hardware Co-Design Platform for Nonvolatile Memory-Based Convolutional Neural Network Accelerators;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-07

2. Performance Analysis of 3D Stacked Memory Architectures in High Performance Computing;2024 4th International Conference on Advance Computing and Innovative Technologies in Engineering (ICACITE);2024-05-14

3. Device-Architecture Co-optimization for RRAM-based In-memory Computing;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24

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