Device-Architecture Co-optimization for RRAM-based In-memory Computing-Reference-Cited by-同舟云学术

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Device-Architecture Co-optimization for RRAM-based In-memory Computing

Published:2023-10-24 Issue: Volume: Page:1-4
ISSN:
Container-title:2023 IEEE 15th International Conference on ASIC (ASICON)
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Author:

Cai Yimao¹,Gao Yi¹,Wang Zongwei¹,Bao Lin¹,Liang Ling¹,Zheng Qilin¹,Wang Cuimei¹,Huang Ru¹

Affiliation:

1. Peking University,School of Integrated Circuits,Beijing,China

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Nova

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10395907/10395930/10396275.pdf?arnumber=10396275

Reference16 articles.

1. Memory materials and devices: From concept to application

2. A Convolution Neural Network Accelerator Design with Weight Mapping and Pipeline Optimization

3. A stable rhombohedral phase in ferroelectric Hf(Zr) ₁₊ _x O ₂ capacitor with ultralow coercive field

4. Edge learning using a fully integrated neuro-inspired memristor chip

5. A crossbar array of magnetoresistive memory devices for in-memory computing

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