Performance Analysis of 3D Stacked Memory Architectures in High Performance Computing
Author:
Affiliation:
1. Arizona State University,School of Electrical, Computer and Energy Engineering,Tempe,USA
2. Kakatiya Institute of Technology and Science,Department of Electronics and Communication Engineering,Warangal,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10616389/10616398/10616405.pdf?arnumber=10616405
Reference16 articles.
1. 3D Stacked Microprocessor: Are We There Yet?
2. 3D-Stacked Memory Architectures for Multi-core Processors
3. An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth
4. Simultaneous Multi-Layer Access
5. HeM3D
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