PRIME

Author:

Chi Ping1,Li Shuangchen1,Xu Cong2,Zhang Tao3,Zhao Jishen1,Liu Yongpan4,Wang Yu4,Xie Yuan1

Affiliation:

1. University of California

2. HP Labs, Palo Alto

3. NVIDIA Corporation

4. Tsinghua University, Beijing, China

Abstract

Processing-in-memory (PIM) is a promising solution to address the "memory wall" challenges for future computer systems. Prior proposed PIM architectures put additional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has showed its potential to be used for main memory. Moreover, with its crossbar array structure, ReRAM can perform matrix-vector multiplication efficiently, and has been widely studied to accelerate neural network (NN) applications. In this work, we propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, a portion of ReRAM crossbar arrays can be configured as accelerators for NN applications or as normal memory for a larger memory space. We provide microarchitecture and circuit designs to enable the morphable functions with an insignificant area overhead. We also design a software/hardware interface for software developers to implement various NNs on PRIME. Benefiting from both the PIM architecture and the efficiency of using ReRAM for NN computation, PRIME distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving. Our experimental results show that, compared with a state-of-the-art neural processing unit design, PRIME improves the performance by ~2360× and the energy consumption by ~895×, across the evaluated machine learning benchmarks.

Publisher

Association for Computing Machinery (ACM)

Cited by 386 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. SAL: Optimizing the Dataflow of Spin-based Architectures for Lightweight Neural Networks;ACM Transactions on Architecture and Code Optimization;2024-09-14

2. Enhancing ConvNets With ConvFIFO: A Crossbar PIM Architecture Based on Kernel-Stationary First-In-First-Out Dataflow;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-09

3. TEFLON: Thermally Efficient Dataflow-aware 3D NoC for Accelerating CNN Inferencing on Manycore PIM Architectures;ACM Transactions on Embedded Computing Systems;2024-08-14

4. ReDy: A Novel ReRAM-centric Dynamic Quantization Approach for Energy-efficient CNNs;Proceedings of the 53rd International Conference on Parallel Processing;2024-08-12

5. CRPIM: An efficient compute-reuse scheme for ReRAM-based Processing-in-Memory DNN accelerators;Journal of Systems Architecture;2024-08

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