Vertical N-Type and P-Type Nanosheet FETs With C-Shaped Channel
Author:
Affiliation:
1. Key Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China
Funder
Vertical Gate-All-Around for Dynamic Random Access Memory (DRAM) and Process Development under Beijing Superstring Academy Memory Technology
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10053598/10035482.pdf?arnumber=10035482
Reference21 articles.
1. Process Technology Variation
2. Simulations of Statistical Variability in n-Type FinFET, Nanowire, and Nanosheet FETs
3. Vertical C-Shaped-Channel Nanosheet FETs Featured With Precise Control of Both Channel-Thickness and Gate-Length
4. (Invited) Epitaxy of (SiGe/Si) Superlattices for the Fabrication of Horizontal Gate-All-Around Nanosheet Transistors
5. Investigation of negative bias temperature instability dependence on fin width of silicon-on-insulator-fin-based field effect transistors
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