High-Performance Gate-all-around Junctionless Vertical-Channel Transistors with the Ultra-low Sub-threshold Swing for Next-generation 4F<sup>2</sup> DRAM-Reference-Cited by-同舟云学术

High-Performance Gate-all-around Junctionless Vertical-Channel Transistors with the Ultra-low Sub-threshold Swing for Next-generation 4F² DRAM

Published:2023-12-09 Issue: Volume:67 Page:1-4
ISSN:
Container-title:2023 International Electron Devices Meeting (IEDM)
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Author:

Yoo Abraham¹,Jiang Yi¹,Qiu Yunsong¹,Zheng Yuhong¹,Yang Chen¹,Feng Daohuan¹,Liao Yucheng¹,Kong Xiangbo¹,Xiao Jianfeng¹,Xie Dongsheng¹,Liu Jinying¹,Chu Jian¹,Ma Di¹,Hu Minrui¹,Zhao Wenli¹,Shao Guangsu¹,Lin Chao¹,Shao Kai¹,Wang Yan¹,Xu Handong¹,Li Zelun¹,Huang Kuoming¹,Xue Xingkun¹,Gu Tingting¹,You Kang¹,Liu Xiang¹,Jeon Jong Sung¹,Si Shufang¹,Tang Yanzhe¹,Liu Mingde¹,Guo Yadong¹,Chen Jintao¹,Zhang Mingtang¹,Jin Xinwen¹,Yang GJ¹,Han DH¹,Park Ted²,Xiao Deyuan¹,Zhao Chao²,Cao Kanyu¹

Affiliation:

1. Chang Xin Memory Technologies, Inc,Hefei,China,230601

2. Beijing Superstring Academy of Memory Technology,Beijing,China,100176

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10413659/10413660/10413667.pdf?arnumber=10413667

Reference8 articles.

1. 1T-1C Dynamic Random Access Memory Status, Challenges, and Prospects

2. Comprehensive Analysis of Gate-Induced Drain Leakage in Vertically Stacked Nanowire FETs: Inversion-Mode Versus Junctionless Mode

3. Insight Into Gate-Induced Drain Leakage in Silicon Nanowire Transistors

4. Vertical N-Type and P-Type Nanosheet FETs With C-Shaped Channel

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