A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFET
Author:
Affiliation:
1. Equally Credited Authors (ECAs)
2. Texas A&M University,College Station,TX,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9772767/9772730/09772868.pdf?arnumber=9772868
Reference7 articles.
1. 6.4 A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology
2. 6.2 A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss
3. A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET
4. 30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET
5. A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET
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