6.2 A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss-Reference-Cited by-同舟云学术

6.2 A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss

Published:2019-02 Issue: Volume: Page:
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Container-title:2019 IEEE International Solid- State Circuits Conference - (ISSCC)
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Author:

LaCroix Marc-Andre,Wong Henry,Liu Yun Hua,Ho Huong,Lebedev Semyon,Krotnev Petar,Nicolescu Dorin Alexandru,Petrov Dmitry,Carvalho Carlos,Alie Stephen,Chong Euhan,Musa Faisal Ahmed,Tonietto Davide

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8656625/8662285/08662322.pdf?arnumber=8662322

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