Balanced Circuit Topologies and Their Applications in Data Movement
Author:
Affiliation:
1. University of Utah,USA
2. Kandou Bus,Switzerland
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9859262/9859267/09859480.pdf?arnumber=9859480
Reference28 articles.
1. A 4× 9Gb/slpJ/b hybrid NRZ/Multi-Tone I/O with crosstalk and ISI reduction for dense interconnects;gharibdoust;IEEE Journal of Solid-State Circuits,2016
2. A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links
3. A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFET
4. A 25Gb/s PAM4 transmitter in 90nm CMOS SOI
5. A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter
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