30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

Author:

Kim Gain,Kull Lukas,Luu Danny,Braendli Matthias,Menolfi Christian,Francese Pier-Andrea,Yueksel Hazar,Aprile Cosimo,Morf Thomas,Kossel Marcel,Cevrero Alessandro,Ozkaya Ilter,Burg Andreas,Toifl Thomas,Leblebici Yusuf

Publisher

IEEE

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21

2. FBMC vs. PAM and DMT for High-Speed Wireline Communication;IEEE Open Journal of Circuits and Systems;2024

3. Efficient PAPR Reduction for Discrete Multi-Tone Signalling in High-Speed Wireline Applications;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

4. A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFET;2022 IEEE Custom Integrated Circuits Conference (CICC);2022-04

5. Spectrally Efficient DMT Operation With BER-Informed Dynamic Bit and Power Loading;IEEE Access;2022

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