A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET-Reference-Cited by-同舟云学术

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A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET

Published:2018-02 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE International Solid - State Circuits Conference - (ISSCC)
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Author:

Upadhyaya Parag,Poon Chi Fung,Lim Siok Wei,Cho Junho,Roldan Arianne,Zhang Wenfeng,Namkoong Jin,Pham Toan,Xu Bruce,Lin Winson,Zhang Hongtao,Narang Nakul,Tan Kee Hian,Zhang Geoff,Frans Yohan,Chang Ken

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8304413/8310156/08310207.pdf?arnumber=8310207

Cited by 53 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation;IEEE Journal of Solid-State Circuits;2024-08

3. A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS;Journal of Semiconductors;2024-06-01

4. A 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based ΔΣ ADC Suitable for DVFS;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

5. Multi-Stage Speculative PAM4 Decision Feedback Equalizer for Short Reach Applications;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

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