Novel CMOS and PTL Based Half Subtractor Designs-Reference-Cited by-同舟云学术

Novel CMOS and PTL Based Half Subtractor Designs

Published:2021-12 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Symposium on Smart Electronic Systems (iSES)
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Author:

Rajput Anju¹,Dua Tripti¹,Kumawat Renu²,Srinivasulu Avireni³

Affiliation:

1. Manipal University,Dept. of Electronics & Communication Engineering,Jaipur,India

2. Manipal University,Dept. of Computer & Communication Engineering,Jaipur,India

3. K. R. Mangalam University,School of Engineering and Technology,Gurugram,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9700979/9700995/09701084.pdf?arnumber=9701084

Reference27 articles.

1. Power Reduction of Half Adder and Half Subtractor Using Different Partial Adiabatic Logic Styles

2. Design and implementation of SET-CMOS hybrid half subtractor

3. Design a Low Power Half-Subtractor Using .90µm CMOS Technology

4. Quantam Gate Implementation of a Novel Reversible Half Adder and Subtractor Circuit;sarma;IEEE International Conference on Intelligent Circuits and Systems(ICICS),2018

5. The Design of Half Subtractor Logic Function based on Non-Linear Directional Coupler;bakhtiar;Journal of Advances in Computer Research,2011

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