Modified Low Power High Speed Approximate Adders For Energy Efficient Arithmetic Applications-Reference-Cited by-同舟云学术

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Modified Low Power High Speed Approximate Adders For Energy Efficient Arithmetic Applications

Published:2023-06-29 Issue: Volume: Page:
ISSN:
Container-title:2023 15th International Conference on Electronics, Computers and Artificial Intelligence (ECAI)
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Author:

Reddy Moola Vamsi Krishna¹,Reddy Nusum Raja Sekhar²,Kumar Pinnepalli Naveen²,Reddy Ramireddy Praneeth Kumar¹,Sarada M.³,Srinivasulu Avireni²^ORCID

Affiliation:

1. Mohan Babu University [Erstwhile Sree Vidyanikethan Eng., Coll.],Dept. of Electronics & Comm.,Sree Sainath Nagar,India

2. Mohan Babu University [Erstwhile Sree Vidyanikethan Engineering College],Dept. of Electronics & Comm,Tirupati,India

3. Vignan's University (VFSTR Deemed to be Uni.),Dept. of Electronics & Comm,Guntur, Vadlamudi,India,517213

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10193876/10193857/10193956.pdf?arnumber=10193956

Reference27 articles.

1. Generalized Analytical Model for Enzymatic Bio-FET Transistors;ravariu;Biosensors (MDPI),2022

2. A Novel 2:1 Multiplexer Based Quaternary Full Adder

3. Accuracy-configurable adder for approximate arithmetic designs

4. Implementation of semi-static and differential null convention logic gates using CNTFET technology;sarada;Romanian Journal of Information Science and Technology,2022

5. QPA: A Quantization-Aware Piecewise Polynomial Approximation Methodology for Hardware-Efficient Implementations

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