Design and implementation of SET-CMOS hybrid half subtractor-Reference-Cited by-同舟云学术

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Design and implementation of SET-CMOS hybrid half subtractor

Published:2014-12 Issue: Volume: Page:
ISSN:
Container-title:2014 Annual IEEE India Conference (INDICON)
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Author:

Ghosh Arpita,Jain Amit,Singh N.B.,Sarkar Subir Kumar

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7016294/7030354/07030405.pdf?arnumber=7030405

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Area Efficient and Low Power Half Subtractor Using Transmission Gate CMOS Logic;2022 IEEE Region 10 Symposium (TENSYMP);2022-07-01

2. Design of Energy Efficient Static Level Restorer Based Half Subtractor using CNFETs;2022 32nd International Conference Radioelektronika (RADIOELEKTRONIKA);2022-04-21

3. Novel CMOS and PTL Based Half Subtractor Designs;2021 IEEE International Symposium on Smart Electronic Systems (iSES);2021-12

4. The design and performance of different nanoelectronic binary multipliers;Journal of Computational Electronics;2021-11-18

5. Memristive-synapse spiking neural networks based on single-electron transistors;Journal of Computational Electronics;2019-12-26

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