Area Efficient and Low Power Half Subtractor Using Transmission Gate CMOS Logic
Author:
Affiliation:
1. Manipal University Jaipur,Electronics & Communication, Engg,Jaipur,India
2. School of Engineering & Technology, K R Mangalam University,Gurugram,India
3. Manipal University Jaipur,Computer & Communication, Engg,Jaipur,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9864330/9864331/09864422.pdf?arnumber=9864422
Reference25 articles.
1. The Design of Half Subtractor Logic Function based on Non-Linear Directional Coupler;bakhtiar;Journal of Advances in Computer Research,2011
2. Implementation of high performance and low leakage half subtractor circuit using AVL technique
3. Design and implementation of SET-CMOS hybrid half subtractor
4. A Novel Design of Half Subtractor using Reversible Feynman Gate in Quantum Dot cellular Automata;rubina;American Journal of Engineering Research,2014
5. Design and Analysis of Power Efficient PTL Half Subtractor Using 120nm Technology;sharma;International Journal of Computer Trends and Technology,2015
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