New Insight into the Aging Induced Retention Time Degraded of Advanced DRAM Technology
Author:
Affiliation:
1. Shanghai Jiao Tong university,National Key Laboratory of Science and Technology on Micro/Nano Fabrication,Shanghai,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9764406/9764408/09764508.pdf?arnumber=9764508
Reference25 articles.
1. Sensing voltage compensation circuit for low-power dram bit-line sense amplifier
2. Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM
3. Overcoming the reliability limitation in the ultimately scaled DRAM using silicon migration technique by hydrogen annealing
4. Superior Improvements in GIDL and Retention by Fluorine Implantation in Saddle-Fin Array Devices for Sub-40-nm DRAM Technology
5. Prediction of Data Retention Time Distribution of DRAM by Physics-Based Statistical Simulation
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1. Understanding Retention Time Distribution in Buried-Channel-Array-Transistors (BCAT) Under Sub-20-nm DRAM Node—Part II: PBTI Aging and Optimization;IEEE Transactions on Electron Devices;2024-08
2. Understanding Retention Time Distribution in Buried-Channel-Array-Transistors (BCAT) Under Sub-20-nm DRAM Node—Part I: Defect-Based Statistical Compact Model;IEEE Transactions on Electron Devices;2024-08
3. Interface Engineering of Trench-Ox for Modern DRAM Devices;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14
4. Cryogenic Body Bias Effect in DRAM Peripheral and Buried-Channel-Array Transistor for Quantum Computing Applications;IEEE Access;2024
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