A 1.97 TFLOPS/W Configurable SRAM-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient AI Chips
Author:
Affiliation:
1. School of Microelectronics Science and Technology, Sun Yat-sen University,Guangzhou,China
Funder
National Natural Science Foundation of China (NSFC)
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10182197.pdf?arnumber=10182197
Reference12 articles.
1. A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations
2. A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications
3. Can programming be liberated from the von Neumann style?
4. A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices
5. A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing
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1. CINEMA: A Configurable Binary Segmentation Based Arithmetic Module for Mixed-Precision In-Memory Acceleration;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. An 11T1C Bit-Level-Sparsity-Aware Computing-in-Memory Macro With Adaptive Conversion Time and Computation Voltage;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
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