A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices-Reference-Cited by-同舟云学术

A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices

Published:2022-02-20 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Wu Ping-Chun¹,Su Jian-Wei²,Chung Yen-Lin¹,Hong Li-Yang¹,Ren Jin-Sheng¹,Chang Fu-Chun¹,Wu Yuan¹,Chen Ho- Yu¹,Lin Chen-Hsun¹,Hsiao Hsu-Ming²,Li Sih-Han²,Sheu Shyh-Shyuan²,Chang Shih-Chieh²,Lo Wei-Chung²,Lo Chung-Chuan¹,Liu Ren-Shuo¹,Hsieh Chih-Cheng¹,Tang Kea-Tiong¹,Wu Chih-I²,Chang Meng-Fan¹

Affiliation:

1. National Tsing Hua University,Hsinchu,Taiwan

2. Industrial Technology Research Institute,Hsinchu,Taiwan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731681.pdf?arnumber=9731681

Reference6 articles.

1. 15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications

2. 15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

3. An S9TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications;chih;ISSCC,2021

4. 16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

5. 24.4 Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation

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