A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications

Author:

Lee Chia-Fu1,Lu Cheng-Han1,Lee Cheng-En1,Mori Haruki1,Fujiwara Hidehiro1,Shih Yi-Chun1,Chou Tan-Li1,Chih Yu-Der1,Chang Tsung-Yung Jonathan1

Affiliation:

1. TSMC,Hsinchu,Taiwan

Publisher

IEEE

Reference5 articles.

Cited by 32 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Trident-CIM: A LUT-Based Compute-in-Memory Macro With Trident Read Bit-Line and Partial Product Pruning;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-05

3. Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing;Science;2024-04-19

4. NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

5. A 1–8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

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