NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA
Funder
PRISM and CHIMES
Semiconductor Research Corporation (SRC)/Defense Advanced Research Projects Agency (DARPA) Joint University Microelectronics Program (JUMP) 2.0 Centers
Samsung
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/8919/10484988/10443264.pdf?arnumber=10443264
Reference57 articles.
1. Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects
2. RRAM for Compute-in-Memory: From Inference to Training
3. 16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications
4. A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs
5. A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations
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