Interface Trap Density of Commercial 1.7 kV SiC Power MOSFETs
Author:
Affiliation:
1. University of Campinas,School of Electrical and Computer Engineering,Campinas,Brazil
2. University of Applied Sciences and Arts Northwestern Switzerland,Institute of Electric Power Systems,Windisch,Switzerland
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10302454/10302463/10302591.pdf?arnumber=10302591
Reference17 articles.
1. SiC/SiO2 interface traps effect on SiC MOSFETs Gate capacitance with biased Drain
2. SiC MOSFET C-V Curves Analysis with Floating Drain Configuration
3. Revisiting MOSFET threshold voltage extraction methods
4. Characterization of Gate-Oxide Degradation Location for SiC MOSFETs Based on the Split C–V Method Under Bias Temperature Instability Conditions
5. Influence of the SiC/SiO2 SiC MOSFET Interface Traps Distribution on C–V Measurements Evaluated by TCAD Simulations
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1. Positive Bias Temperature Instability in SiC-Based Power MOSFETs;Micromachines;2024-06-30
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