Characterization of Gate-Oxide Degradation Location for SiC MOSFETs Based on the Split <i>C–V</i> Method Under Bias Temperature Instability Conditions-Reference-Cited by-同舟云学术

Characterization of Gate-Oxide Degradation Location for SiC MOSFETs Based on the Split C–V Method Under Bias Temperature Instability Conditions

Published:2023-05 Issue:5 Volume:38 Page:6081-6093
ISSN:0885-8993
Container-title:IEEE Transactions on Power Electronics
language:
Short-container-title:IEEE Trans. Power Electron.

Author:

Cai Yumeng¹^ORCID,Chen Cong¹,Zhao Zhibin¹^ORCID,Sun Peng¹^ORCID,Li Xuebao¹^ORCID,Zhang Manhong¹^ORCID,Wang Hui²^ORCID,Chen Zhong²^ORCID,Nee Hans-Peter³^ORCID

Affiliation:

1. School of Electrical and Electronic Engineering, North China Electric Power University, Beijing, China

2. Department of Electrical Engineering, University of Arkansas, Fayetteville, AR, USA

3. KTH Royal Institute of Technology, Stockholm, Sweden

Funder

Science and Technology Project of State Grid Corporation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/63/10067244/10024796.pdf?arnumber=10024796

Reference34 articles.

1. Contribution to the study of the SiC MOSFETs gate oxide;salvadó,2018

2. Measurement and analysis of SiC-MOSFET threshold voltage shift

3. A Physical Explanation of Threshold Voltage Drift of SiC MOSFET Induced by Gate Switching

4. Dynamic Gate Stress Induced Threshold Voltage Drift of Silicon Carbide MOSFET

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