SiC MOSFET C-V Curves Analysis with Floating Drain Configuration

Abstract

SiC MOSFETs have already replaced silicon-based device in power applications, even if some technological issues are still not solved. Among others, the complex traps distribution at SiC/SiO2 interface is of foremost importance. Interface traps affect the overall device behavior, modifying channel mobility and introducing hysteresis. In this work, the capacitance behavior, when the Drain terminal is floating, is studied through numerical analysis. The effects of traps distribution and its properties on such curves has been studied along with temperature effects. Experimental curves are carried out at various temperatures and compared to the same trends of numerical results.