Affiliation:
1. University Federico II
2. University of Naples Federico II
3. Kyoto University of Advanced Science
Abstract
In this paper, SiC MOSFETs capacitance is monitored when a DC bias is applied between Drain and Source. The arising capacitance exhibits a sharp peak in the inversion region which is related to the SiC/SiO2 interface traps properties. Temperature effects on such peak are investigated using both experimental and numerical results. The peak shifts toward lower Gate voltage as temperature increases, in agreement with the threshold voltage reduction at higher temperature.
Publisher
Trans Tech Publications, Ltd.
Subject
Mechanical Engineering,Mechanics of Materials,Condensed Matter Physics,General Materials Science
Reference18 articles.
1. B. J. Baliga, Fundamentals of power semiconductor devices, Springer Science & Business Media, (2010).
2. Comparison of trapping–detrapping properties of mobile charge in alkali contaminated metal‐oxide‐silicon carbide structures;Raynaud;Applied Physics Letters
3. D. Peters et al., Investigation of threshold voltage stability of SiC MOSFETs, ISPSD, (2018).
4. Intrinsic SiC/SiO2 Interface States;Afanasev;physica status solidi (a)
5. Schroder, D.K. Semiconductor Material and Device Characterization, 3rd ed.; Wiley: Hoboken, NJ, USA, (2006)
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Frequency Investigation of SiC MOSFETs C-V Curves with Biased Drain;Solid State Phenomena;2024-08-23
2. SiC MOSFETs capacitance study;e-Prime - Advances in Electrical Engineering, Electronics and Energy;2023-09