ROUTABILITY-DRIVEN PACKING: METRICS AND ALGORITHMS FOR CLUSTER-BASED FPGAs-Reference-Cited by-同舟云学术

ROUTABILITY-DRIVEN PACKING: METRICS AND ALGORITHMS FOR CLUSTER-BASED FPGAs

Published:2004-02 Issue:01 Volume:13 Page:77-100
ISSN:0218-1266
Container-title:Journal of Circuits, Systems and Computers
language:en
Short-container-title:J CIRCUIT SYST COMP

Author:

BOZORGZADEH E.¹,MEMIK S. OGRENCI²,YANG X.³,SARRAFZADEH M.⁴

Affiliation:

1. Computer Science Department, University of California, Irvine, CA 92697-3425, USA

2. Department of Electrical and Computer Engineering, Northwestern University, Evasnton, IL 60201, USA

3. Synplicity Inc., 600 W California Ave, Sunnyvale, CA 94086, USA

4. Computer Science Department, University of California, Los Angeles (UCLA), 3531C Boelter Hall, Los Angeles, CA 90095, USA

Abstract

Most of the FPGA's area and delay are due to routing. Considering routability at earlier steps of the CAD flow would both yield better quality and faster design process. In this paper, we discuss the metrics that affect routability in packing logic into clusters. We are presenting a routability-driven clustering method for cluster-based FPGAs. Our method packs LUTs into logic clusters while incorporating routability metrics into a cost function. Based on our routability model, the routability in timing-driven packing algorithm is analyzed. We integrate our routability model into a timing-driven packing algorithm. Our method yields up to 50% improvement in terms of the minimum number of routing tracks compared to VPack (16.5% on average). The average routing area improvement is 27% over VPack and 12% over t-VPack.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Link

https://www.worldscientific.com/doi/pdf/10.1142/S0218126604001222

Reference9 articles.

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