LUT-based FPGA technology mapping under arbitrary net-delay models-Reference-Cited by-同舟云学术

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LUT-based FPGA technology mapping under arbitrary net-delay models

Published:1994-07 Issue:4 Volume:18 Page:507-516
ISSN:0097-8493
Container-title:Computers & Graphics
language:en
Short-container-title:Computers & Graphics

Author:

Cong Jason,Ding Yuzheng,Gao Tong,Chen Kuang-Chien

Publisher

Elsevier BV

Subject

Computer Graphics and Computer-Aided Design,Human-Computer Interaction,General Engineering

Reference17 articles.

1. The Programmable Gate Array Data Book;Xilinx,1992

2. A CAD system for the design of field programmable gate arrays;Hill,1991

3. Logic synthesis algorithms for programmable gate arrays;Murgai,1990

4. Improved logic synthesis algorithms for table look up architectures;Murgai,1991

5. Chortle-crf: Fast technology mapping for lookup table-based FPGAs;Francis,1991

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Technology Mapping;Reconfigurable Computing;2008

2. ROUTABILITY-DRIVEN PACKING: METRICS AND ALGORITHMS FOR CLUSTER-BASED FPGAs;Journal of Circuits, Systems and Computers;2004-02

3. Effective and efficient FPGA synthesis through general functional decomposition;Journal of Systems Architecture;2003-09

4. Technology mapping of heterogeneous LUT-based FPGAs;Field-Programmable Logic and Applications;1997

5. Combinational logic synthesis for LUT based field programmable gate arrays;ACM Transactions on Design Automation of Electronic Systems;1996-04

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