Technology mapping of heterogeneous LUT-based FPGAs
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/3-540-63465-7_227
Reference22 articles.
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3. R. J. Francis, J. Rose, and Z. Vranesic, “Technology mapping of lookup table-based FPGAs for performance,” in IEEE/ACM International Conference on ComputerAided Design, pp. 568–571, 1991.
4. R. Murgai, Y. Nishiza,ki, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Logic synthesis for programmable gate arrays,” in 27th Design Automation Conference, pp. 620–625, 1990.
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1. Reconfigurable computing;ACM Computing Surveys;2002-06
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