Author:
Francis Robert,Rose Jonathan,Vranesic Zvonko
Cited by
57 articles.
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1. FPGA Technology Mapping with Adaptive Gate Decomposition;Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays;2023-02-12
2. Improving LUT-based optimization for ASICs;Proceedings of the 59th ACM/IEEE Design Automation Conference;2022-07-10
3. LUT-Based Optimization For ASIC Design Flow;2021 58th ACM/IEEE Design Automation Conference (DAC);2021-12-05
4. An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs;Microelectronics Reliability;2017-08
5. LUT based realization of fixed-point multipliers targeting state-of-art FPGAs;Design Automation for Embedded Systems;2017-03-10