Breaking Boundaries: Optimizing FPGA CAD with Flexible and Multi-threaded Re-Clustering-Reference-Cited by-同舟云学术

Breaking Boundaries: Optimizing FPGA CAD with Flexible and Multi-threaded Re-Clustering

Published:2023-06-14 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
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Author:

Elgammal Mohamed A.¹^ORCID,Betz Vaughn¹^ORCID

Affiliation:

1. University of Toronto, Canada

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3597031.3597054

Reference26 articles.

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2. Ziad Abuowaimer 2018. GPlace3. 0: Routability-driven analytic placer for UltraScale FPGA architectures. (TODAES) 23, 5 ( 2018 ), 1–33. Ziad Abuowaimer 2018. GPlace3. 0: Routability-driven analytic placer for UltraScale FPGA architectures. (TODAES) 23, 5 (2018), 1–33.

3. Andrew Boutros 2020. Beyond peak performance: Comparing the real performance of AI-optimized FPGAs and GPUs. In (ICFPT) . IEEE , 10–19. Andrew Boutros 2020. Beyond peak performance: Comparing the real performance of AI-optimized FPGAs and GPUs. In (ICFPT). IEEE, 10–19.

4. ROUTABILITY-DRIVEN PACKING: METRICS AND ALGORITHMS FOR CLUSTER-BASED FPGAs

5. RPack

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