Multi‐objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs-Reference-Cited by-同舟云学术

Multi‐objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs

Published:2019-02-19 Issue:4 Volume:13 Page:273-281
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Wang Yuan¹,Trefzer Martin A.²^ORCID,Bale Simon J.²,Walker James A.²,Tyrrell Andy M.²

Affiliation:

1. School of Engineering and TechnologyUniversity of HertfordshireHatfieldUK

2. Department of Electronic EngineeringUniversity of YorkYorkUK

Funder

Engineering and Physical Sciences Research Council

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2018.5115

Reference32 articles.

1. Betz V. Rose J.: ‘Cluster‐based logic blocks for FPGAs: area‐efficiency vs. input sharing and size’.Proc. of CICC 97 – Custom Integrated Circuits Conf. Santa Clara CA USA 1997 pp.551–554

2. CAD Tools: Packing and Placement

3. Singh A. Marek‐Sadowska M.: ‘Efficient circuit clustering for area and power reduction in FPGAs’.FPGA ‘02 Proc. of the 2002 ACM/SIGDA Tenth Int. Symp. on Field‐Programmable Gate Arrays Monterey CA USA 2002 pp.59–66

4. A fast and elitist multiobjective genetic algorithm: NSGA-II

5. Marquardt A.S. Betz V. Rose J.: ‘Using cluster‐based logic blocks and timing‐driven packing to improve FPGA speed and density’.FPGA ‘99 Proc. of the 1999 ACM/SIGDA Seventh Int. Symp. on Field Programmable Gate Arrays Monterey CA USA 1999 pp.37–46

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