How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance

Author:

Vercruyce DriesORCID,Vansteenkiste Elias,Stroobandt Dirk

Funder

European Commission in the Context of the H2020-FETHPC EXTRA Project

Ph.D. Grant of the Research Foundation Flanders (FWO)

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Multi-Die Heterogeneous FPGAs;Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding;2022-11-03

2. Optimizing open-source FPGA CAD tools;2022 IEEE High Performance Extreme Computing Conference (HPEC);2022-09-19

3. Accelerating FPGA Routing Through Algorithmic Enhancements and Connection-aware Parallelization;ACM Transactions on Reconfigurable Technology and Systems;2020-10

4. VTR 8;ACM Transactions on Reconfigurable Technology and Systems;2020-06-30

5. A Circuit Optimization Method of Improved Lookup Table for Highly Efficient Resource Utilization;J ELECTRON INF TECHN;2019

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