Multi-Die Heterogeneous FPGAs-Reference-Cited by-同舟云学术

Multi-Die Heterogeneous FPGAs

Published:2022-11-03 Issue: Volume: Page:
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Container-title:Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding
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Author:

Raikar Raveena¹,Stroobandt Dirk¹

Affiliation:

1. Ghent University, Ghent, Belgium

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3557988.3569711

Reference9 articles.

1. Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research

2. Andrew B. Kahng , Jens Lienig , Igor L. Markov , and Jin Hu. 2011. VLSI Physical Design: From Graph Partitioning to Timing Closure . ( 1 st ed.). Springer Publishing Company, Inc orporated. isbn: 9789048 1959 09. Andrew B. Kahng, Jens Lienig, Igor L. Markov, and Jin Hu. 2011. VLSI Physical Design: From Graph Partitioning to Timing Closure. (1st ed.). Springer Publishing Company, Incorporated. isbn: 9789048195909.

3. Multilevel hypergraph partitioning: applications in VLSI domain

4. George Karypis and Vipin Kumar. 1998. "hMETIS 1.5: A hypergraph partitioning package". http://www.cs.umn.edu/metis. Dept. Comput. Sci. Eng. Army HPC Res. Center Univ.Minnesota Minneapolis MN USA Tech. Rep. (Nov. 1998). George Karypis and Vipin Kumar. 1998. "hMETIS 1.5: A hypergraph partitioning package". http://www.cs.umn.edu/metis. Dept. Comput. Sci. Eng. Army HPC Res. Center Univ.Minnesota Minneapolis MN USA Tech. Rep. (Nov. 1998).

5. VTR 8

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