Challenges and Solutions of Replacement Metal Gate Patterning to Enable Gate-all-Around Device Scaling-Reference-Cited by-同舟云学术

Challenges and Solutions of Replacement Metal Gate Patterning to Enable Gate-all-Around Device Scaling

Published:2021-02 Issue: Volume:314 Page:119-126
ISSN:1662-9779
Container-title:Solid State Phenomena
language:
Short-container-title:SSP

Author:

Oniki Yusuke¹,Ragnarsson Lars Åke¹,Iino Hideaki²,Cott Daire¹,Chan Boon Teik¹,Sebaai Farid³,Hopf Toby¹,Dekkers Harold¹,Dentoni Litta Eugenio¹,Sánchez Efrain Altamirano¹,Holsteyns Frank¹,Horiguchi Naoto¹

Affiliation:

1. IMEC

2. Kurita Water Industries Ltd.

3. IMEC Interuniversity Microelectronics Center

Abstract

This paper addresses challenges and solutions of replacement metal gate of gate-all-around nanosheet devices. The unit process and integration solutions for the metal gate patterning as well as interface dipole patterning to offer multiple threshold voltage have been developed. The challenges of long channel device integration are also discussed.

Publisher

Trans Tech Publications, Ltd.

Subject

Condensed Matter Physics,General Materials Science,Atomic and Molecular Physics, and Optics

Link

https://www.scientific.net/SSP.314.119.pdf

Reference16 articles.

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3. N. Loubet et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET, 2017 Symposium on VLSI Technology Digest of Technical Papers, (2017) T230-T231.

4. H. Mertens et al. Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration, IEDM Tech. Dig. (2017) 828.

5. Y. Oniki et al. Selective Etches for Gate-All-Around (GAA) Device Integration: Opportunities and Challenges, ECS Trans. 92 (2019) 3-12.

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