Improvement of depth of focus control using wafer geometry

Author:

Lee Honggoo,Lee Jongsu,Kim Sangmin,Lee Changhwan,Han Sangjun,Kim Myoungsoo,Kwon Wontaik,Park Sung-Ki,Veeraraghavan Sathish,Kim JH,Awasthi Amartya,Byeon Jungho,Mueller Dieter,Sinha Jaydeep

Publisher

SPIE

Reference7 articles.

1. Lithography Chapter, International Technology Roadmap for Semiconductors (ITRS), 2013, http://www.itrs.net/Links/2013ITRS/2013Chapters/2013Litho.pdf.

2. Approaching New Metrics for Wafer Flatness: An Investigation of the Lithography Consequences of Wafer Non-Flatness;Valley,2004

3. Wafer Geometry and Lithography Focus Performance for Advanced Nodes – Preliminary Results;Brinkhof,2011

4. International Technology Roadmap for Semiconductors, 2011 Edition, Table LITH2. http://www.itrs.net/Links/2012ITRS/2012Tables/Litho_2012Tables.xlsx

5. Mechanics Modeling of Nanotopography Effects on CMP;Vukkadala,2010

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