Device overlay root cause process detection using patterned wafer geometry information-Reference-Cited by-同舟云学术

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Device overlay root cause process detection using patterned wafer geometry information

Published:2024-04-10 Issue: Volume:8 Page:67
ISSN:
Container-title:Metrology, Inspection, and Process Control XXXVIII
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Author:

Ham Sejung,Song Youngkwang,Lee Cheolwoo,Kim Mingyu,Hyun Minsung,Park Sunghyun,Kim Moonsoup,Lee Jeonghoon,Oh Nanglyeom,Park Sunglyul,Choi Dongsub

Publisher

SPIE

Reference13 articles.

1. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices;Lee,2015

2. Monitoring process-induced overlay errors through high resolution wafer geometry measurements;Turner,2014

3. Patterned wafer geometry grouping for improved overlay control;Lee,2017

4. Patterned wafer geometry (PWG) metrology for improving process-induced overlay and focus problems;Brunner,2016

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