Understanding the factors affecting contact resistance in nanowire field effect transistors (NWFETs) to improve nanoscale contacts for future scaling
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Published:2022-07-14
Issue:2
Volume:132
Page:024302
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ISSN:0021-8979
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Container-title:Journal of Applied Physics
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language:en
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Short-container-title:Journal of Applied Physics
Author:
Ramesh S.12ORCID, Ivanov Ts.2ORCID, Sibaja-Hernandez A.2ORCID, Alian A.2, Camerotto E.3, Milenin A.2, Pinna N.2ORCID, El Kazzi S.2ORCID, Lin D.2, Lagrain P.2, Favia P.2, Bender H.2, Collaert N.2, De Meyer K.12
Affiliation:
1. KU Leuven, ESAT, Kasteelpark Arenberg 10, 3001 Leuven, Belgium 2. IMEC, Kapeldreef 75, 3001 Leuven, Belgium 3. Lam Research Belgium, Kapeldreef 75, 3001 Leuven, Belgium
Abstract
In this paper, dry etched vertical nanowires (VNWs) are used in transmission line/transfer length analysis to study the contacts of gate-all-around devices for future technology nodes. VNW resistors with Mo and Pd based metal stack contacts to p-InGaAs show Schottky behavior, unlike the planar counterpart. The resistance for Mo contact is higher than Pd, however, Pd was found to form an alloy with InGaAs at temperatures as low as 190 °C, and the length of Pd diffusion into the InGaAs increased at smaller NW dimensions, hindering future scalability. The minimum extracted specific contact resistivity ( ρC) values are 1.6 × 10−5 Ω cm2 (Mo) and 4.2 × 10−6 Ω cm2 (Pd) for a doping level of 1 × 1019 cm−3. An apparent dependence of ρC on the NW diameter was also observed. This has been attributed to the surface states under the un-gated region of NW devices and found to dominate at smaller diameters. An analytical model to account for such geometrical effects has also been developed and validated with technology computer-aided design simulations. The analysis presented in this paper effectively captures the 3D aspects of an NW contact at nanoscale dimensions and can be applied irrespective of the semiconductor and contact metal used.
Subject
General Physics and Astronomy
Reference56 articles.
1. High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates 2. N. Waldron, S. Sioncke, J. Franco, L. Nyns, A. Vais, X. Zhou, H. C. Lin, G. Boccardi, J. W. Maes, Q. Xie, M. Givens, F. Tang, X. Jiang, E. Chiu, A. Opdebeeck, C. Merckling, F. Sebaai, D. van Dorp, L. Teugels, A. S. Hernandez, K. D. Meyer, K. Barla, N. Collaert, and Y. V. Thean, “Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200 μS/μm at 50 nm Lg using a replacement Fin RMG flow,” in 2015 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2015), pp. 31.1.1–31.1.4. 3. X. Zhou, N. Waldron, G. Boccardi, F. Sebaai, C. Merckling, G. Eneman, S. Sioncke, L. Nyns, A. Opdebeeck, J. W. Maes, Q. Xie, M. Givens, F. Tang, X. Jiang, W. Guo, B. Kunert, L. Teugels, K. Devriendt, A. S. Hernandez, J. Franco, D. van Dorp, K. Barla, N. Collaert, and A. V. Y. Thean, “Scalability of InGaAs gate-all-around FET integrated on 300 mm Si platform: Demonstration of channel width down to 7 nm and Lg down to 36nm,” in 2016 IEEE Symposium on VLSI Technology (IEEE, 2016), pp. 1–2. 4. H. Mertens, R. Ritzenthaler, H. Arimura, J. Franco, F. Sebaai, A. Hikavyy, B. J. Pawlak, V. Machkaoutsan, K. Devriendt, D. Tsvetanova, A. P. Milenin, L. Witters, A. Dangol, E. Vancoille, H. Bender, M. Badaroglu, F. Holsteyns, K. Barla, D. Mocuta, N. Horiguchi, and A. V. Y. Thean, “Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal,” in 2015 Symposium on VLSI Technology (VLSI Technology) (IEEE, 2015), pp. T142–T143. 5. L. Witters, J. Mitard, R. Loo, S. Demuynck, S. A. Chew, T. Schram, Z. Tao, A. Hikavyy, J. W. Sun, A. P. Milenin, H. Mertens, C. Vrancken, P. Favia, M. Schaekers, H. Bender, N. Horiguchi, R. Langer, K. Barla, D. Mocuta, N. Collaert, and A. V. Y. Thean, “Strained germanium quantum well p-FinFETs fabricated on 45 nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect,” in 2015 Symposium on VLSI Technology (VLSI Technology) (IEEE, 2015), pp. T56–T57.
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