Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer-Reference-Cited by-同舟云学术

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Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer

Published:2019-01-28 Issue:1 Volume:14 Page:
ISSN:1931-7573
Container-title:Nanoscale Research Letters
language:en
Short-container-title:Nanoscale Res Lett

Author:

Wang Zhuo,Yuan Zhangyi’an,Zhou Xin,Qiao Ming,Li Zhaoji,Zhang Bo

Funder

National Natural Science Foundation of China

China Postdoctoral Science Foundation Funded Project

Natural Science Foundation of Guangdong Province

Applied Fundamental Research Project of Sichuan Province

Fundamental Research Funds for the Central Universities

Publisher

Springer Science and Business Media LLC

Subject

Condensed Matter Physics,General Materials Science

Link

http://link.springer.com/content/pdf/10.1186/s11671-019-2866-5.pdf

Reference21 articles.

1. Disney D, Chan W, Lam R, Blattner R, Ma S, Seng W, Chen J-W, Cornell M, Williams R (2008) 60 V lateral trench MOSFET in 0.35 μm technology. Proc ISPSD:24–27. https://doi.org/10.1109/ISPSD.2008.4538888

2. Erlbacher T, Bauer AJ, Frey L (2010) Reduced on resistance in LDMOS devices by integrating trench gates into planar technology. IEEE Electron Device Lett. 31(5):464–466. https://doi.org/10.1109/LED.2010.2043049

3. Shimamoto S, Yanagida Y, Shirakawa S, Miyakoshi K, Imai T, Oshima T, Sakano J, Wada S (2011) High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology. Proc ISPSD:44–47. https://doi.org/10.1109/ISPSD.2011.5890786

4. Fujii H, Tokumitsu S, Mori T, Yamashita T, Maruyama T, Maruyama T, Maruyama Y, Nishimoto S, Arie H, Kubi S, Ipposhi T (2017) A 90nm bulk BiCDMOS platform technology with 15–80V LD-MOSFETs for automotive applications. Proc ISPSD:73–76. https://doi.org/10.23919/ISPSD.2017.7988896.

5. Huang T-Y, Liao W-Y, Yang C-Y, Huang C-H, Yeh W-CV, Huang C-F, Lo K-H, Chiu C-W, Kao T-C, Su H-D, Chang K-C (2014) 0.18 um BCD technology with best-in-class LDMOS from 6 V to 45 V. Proc ISPSD:179–181. https://doi.org/10.1109/ISPSD.2014.6856005

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