On the Design Principles of 3-D RESURF-Enhanced RF SOI LDMOSFETs: Gate Geometry Optimization and Rescaling
Author:
Affiliation:
1. Department of Engineering, Oatley Laboratory, University of Cambridge, Cambridge, U.K
Funder
Engineering Research Scholarship from the Institution of Electrical Engineers, U.K
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9967813/09954202.pdf?arnumber=9954202
Reference45 articles.
1. Modeling and Characterization of Effects of Dummy-Gate Bias on LDMOSFETs
2. Experimental comparison of RF power LDMOSFETs on thin-film SOI and bulk silicon
3. Improvement the Breakdown Voltage and the On-resistance in the LDMOSFET: Double Buried Metal Layers Structure
4. Analysis of low-voltage super-junction LDMOS structures on thin-SOI substrates
5. Folded gate LDMOS transistor with low on-resistance and high transconductance
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