Reduced On Resistance in LDMOS Devices by Integrating Trench Gates Into Planar Technology-Reference-Cited by-同舟云学术

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Reduced On Resistance in LDMOS Devices by Integrating Trench Gates Into Planar Technology

Published:2010-05 Issue:5 Volume:31 Page:464-466
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Erlbacher Tobias¹,Bauer Anton J.¹,Frey Lothar¹

Affiliation:

1. Fraunhofer Institute for Integrated Systems and Device Technology (IISB), Erlangen, Germany

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/55/5453316/05437265.pdf?arnumber=5437265

Cited by 36 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Charge Plasma Based Dual Buried Gates Power MOSFET with Improved Figure of Merits;Silicon;2024-05-31

2. A novel substrate Voltage-assisted RESURF technique in SOI LDMOS with a heavily doped drift region;Solid-State Electronics;2023-09

3. Multi-dimensional accumulation gate LDMOS with ultra-low specific on-resistance;Microelectronics Journal;2023-08

4. A FIN-LDMOS with Bulk Electron Accumulation Effect;Micromachines;2023-06-10

5. A Uni-gate vertical power MOSFET with improved figure of Merits: Design and analysis;Alexandria Engineering Journal;2023-03

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