Compatibility Challenges for High-ĸ Materials Integration into CMOS Technology

Abstract

AbstractIn addition to meeting the formidable challenges of replacing the nearly perfect SiO2 dielectric, a new dielectric ideally needs to replace SiO2 with minimal rearrangement of the complementary metal oxide semiconductor (CMOS) process flow. In this article, we outline the essential materials-integration issues that arise out of the technical requirements for minimizing changes to future process technologies. These include interfacial layer formation, film microstructure, deposition technologies, and electrical performance challenges such as trapped charge and the mobility degradation associated with any replacement material. Integration of the high-ĸ materials currently under consideration presents a significant challenge for materials scientists and engineers in industry and academia.