VLSI Implementation of Vedic Multiplier
Author:
Publisher
Wiley
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1002/9781119761785.ch2
Reference27 articles.
1. A Time‐Area‐Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics;Thapliyal H.;ESA/VLS,2004
2. Low‐cost serial multipliers for high‐speed specialized processors;Ciminiera L.;The Proceedings IEEE (Computers and Digital Techniques),1988
3. Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers
4. Ramalatha M. Dayalan K. D. Dharani P. &Priya S. D.(2009 July).High‐speed energy efficientALUdesign using Vedic multiplication techniques. In International Conference on Advances in Computational Tools for Engineering Applications 2009 IEEE (pp.600‐603).
5. Tiwari H. D. Gankhuyag G. Kim C. M. &Cho Y. B.(2008 November).Multiplier design based on ancient Indian Vedic Mathematics. In InternationalSoCDesign Conference 2008 IEEE(Vol. 2 pp.II‐65).
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1. An area efficient vedic multiplier for FFT processor implementation using 4-2 compressor adder;International Journal of Electronics;2023-11-06
2. FPGA design of arithmetic optimised APT-VDF using reusable Vedic multiplier with simplified combinational logics for medical signal denoising;International Journal of Electronics;2022-12-05
3. Design of High Speed, Low Power 16x16 Vedic Multiplier With Adiabatic Logic;2022 8th International Conference on Smart Structures and Systems (ICSSS);2022-04-21
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