Design of High Speed, Low Power 16x16 Vedic Multiplier With Adiabatic Logic
Author:
Affiliation:
1. Saveetha Engineering College,Department of ECE,Chennai
2. Loyola ICAM College of Engineering and Technology,Department of ECE,Chennai
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9782157/9782158/09782274.pdf?arnumber=9782274
Reference21 articles.
1. An efficient design of Vedic multiplier using ripple carry adder in Quantum-dot Cellular Automata
2. Implementation of Normal Urdhva Tiryakbhayam Multiplier in VLSI
3. ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics
4. Gate diffusion input based 4‐bit Vedic multiplier design
5. Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique
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