Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_19980306?crawler=true&mimetype=application/pdf
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1. A 54*54-b regularly structured tree multiplier
2. Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology
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