Author:
Ramalatha M.,Dayalan K. Deena,Dharani P.,Priya S. Deborah
Cited by
19 articles.
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1. Design of energy efficient N-bit vedic multiplier for low power hardware architecture;International Journal of Electronics;2024-07-28
2. Impact of Clock-Gating on ALU Optimized RISC-V Microarchitectures for Low Power Applications;2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2024-05-17
3. High Speed 64 Bit Vedic & Booth Multiplier Implementation Using FPGA;2024 3rd International Conference on Artificial Intelligence For Internet of Things (AIIoT);2024-05-03
4. Implementation of Efficient Vedic Multiplier and Its Performance Evaluation;Journal of Circuits, Systems and Computers;2023-09-07
5. FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders;Engineering, Technology & Applied Science Research;2023-06-02