Design of energy efficient N-bit vedic multiplier for low power hardware architecture
Author:
Affiliation:
1. Department of Electronics and Communication Engineering, M.Kumarasamy College of Engineering (Autonomous), Karur, India
Publisher
Informa UK Limited
Link
https://www.tandfonline.com/doi/pdf/10.1080/00207217.2024.2382494
Reference29 articles.
1. An area efficient vedic multiplier for FFT processor implementation using 4-2 compressor adder
2. Design and analysis of High-Speed Low-Power Vedic Multiplier with 3-1-1-2 compressor Using Reversible Logic gates
3. Performance analysis of Vedic mathematics algorithms on re-configurable hardware platform
4. FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders
5. Optimized vedic multiplier using low power 13T hybrid full adder
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