Author:
Ciminiera L.,Valenzano A.
Publisher
Institution of Engineering and Technology (IET)
Subject
General Engineering,General Computer Science
Cited by
6 articles.
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1. VLSI Implementation of Vedic Multiplier;Design and Development of Efficient Energy Systems;2021-04-15
2. VLSI-Oriented Architecture for Two's Complement Serial-Parallel Multiplication without Speed Penalty;2007 International Conference on Computational Science and its Applications (ICCSA 2007);2007-08
3. Two's-complement fast serial-parallel multiplier;IEE Proceedings - Circuits, Devices and Systems;1995
4. Radix-2nmultiplier structures: a structured design methodology;IEE Proceedings E (Computers and Digital Techniques);1993-07
5. Fault-tolerant serial-parallel multiplier;IEE Proceedings E Computers and Digital Techniques;1991