REAL

Author:

Tiwari Sakshi1ORCID,Tuli Shreshth1,Ahmad Isaar1,Agarwal Ayushi1,Panda Preeti Ranjan1,Subramoney Sreenivas2

Affiliation:

1. Indian Institute of Technology Delhi, New Delhi, India

2. Microarchitecture Research Lab, Intel, Bengaluru, India

Abstract

Shared last level caches (LLC) of multicore systems-on-chip are subject to a significant amount of contention over a limited bandwidth, resulting in major performance bottlenecks that make the issue a first-order concern in modern multiprocessor systems-on-chip. Even though shared cache space partitioning has been extensively studied in the past, the problem of cache bandwidth partitioning has not received sufficient attention. We demonstrate the occurrence of such contention and the resulting impact on the overall system performance. To address the issue, we perform detailed simulations to study the impact of different parameters and propose a novel cache bandwidth partitioning technique, called REAL , that arbitrates among cache access requests originating from different processor cores. It monitors the LLC access patterns to dynamically assign a priority value to each core. Experimental results on different mixes of benchmarks show up to 2.13× overall system speedup over baseline policies, with minimal impact on energy.

Funder

Semiconductor Research Corporation

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

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