A fast thermal-aware fixed-outline floorplanning methodology based on analytical models

Author:

Lin Jai-Ming1,Chen Tai-Ting1,Chang Yen-Fu1,Chang Wei-Yi1,Shyu Ya-Ting2,Chang Yeong-Jar2,Lu Juin-Ming2

Affiliation:

1. National Cheng Kung University, Tainan, Taiwan

2. Industrial Technology Research Institute, Hsinchu, Taiwan

Publisher

ACM

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Fast power density aware three‐dimensional integrated circuit floorplanning for hard macroblocks using best operator combination genetic algorithm;International Journal of Circuit Theory and Applications;2023-05-29

2. Thermal-Aware SoC Macro Placement and Multi-chip Module Design Optimization with Bayesian Optimization;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05

3. TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04

4. Progress of Placement Optimization for Accelerating VLSI Physical Design;Electronics;2023-01-09

5. Generalizable Floorplanner through Corner Block List Representation and Hypergraph Embedding;Proceedings of the 28th ACM SIGKDD Conference on Knowledge Discovery and Data Mining;2022-08-14

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